Peer-Reviewed Journal Details
Mandatory Fields
Podsiadlik, T;Farrell, R
2014
October
IEEE Transactions on Circuits and Systems II: Express Briefs
Time-Interleaved Sigma Delta Modulators for FPGAs
Published
6 ()
Optional Fields
61
808
812
This brief describes and analyzes a technique of increasing a sampling rate in a sigma-delta (Sigma Delta) modulator based on a discrete-time description, which is an extension of existing techniques of parallelization. The limitations in the signal-to-noise ratio and the maximum increase of the sampling rate in a digital system are explained, and a structure of a low-pass S. modulator characterized by a short critical path is used in this brief to validate the technique. An implementation of a modulator shows the increase in the sampling rate from 100 to 400 MHz.
PISCATAWAY
1549-7747
10.1109/TCSII.2014.2345293
Grant Details