In modern radio frequency (RF) transceivers the power amplifier (PA) is a central component in terms of power consumption. Achieving efficient performance in this component results in the PA output signal becoming distorted. Linearisation can be performed using techniques such as Digital Pre-Distortion (DPD). The pre-distorter operation of a DPD system involves the constant computation of a distorted signal to ensure linear operation of the nonlinear power amplifier. In this work a novel polynomial evaluation scheme is proposed to optimise the pre-distorter operation within a DPD system. Improvements to latency and hardware requirements are possible with new techniques. Validation of the proposed design was conducted using FPGA implementations and compared to incumbent pipelined solutions for both low latency and hardware efficiency. The proposed method indicated hardware savings of 67.8%, while operating 58.7% faster, compared to an existing implementation.